A Power Management Methodology for High-Level Synthesis

POWER AND TIMING MODELLING, OPTIMISATION AND SIMULATION Leakage current aware high-level estimation for VLSI circuits

The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via powergating is effective to reduce leakage power, but it introduces power-up current that affects the circuit reliability. The authors present an in-depth study on high-level modelling of power-up current and leakage current in ...

Power Management in High-Level Synthesis - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

In this paper, we present a power-management methodology targeted toward high-level synthesis of datadominated behavioral descriptions. It is founded on the observation that variable assignment can significantly affect power-management opportunities in the synthesized architecture, i.e., variable assignment determines whether or not spurious operations get executed by functional units in the ar...

Smart Energy Management and Low-Power Design of Sensor and Actua- tor Nodes on Algorithmic Level for Self-Powered Sensorial Materials and Robotics

We propose and demonstrate a design methodology for embedded systems satisfying low power requirements suitable for self-powered sensor and actuator nodes. This design methodology focuses on 1. smart energy management at runtime and 2. application-specific System-On-Chip (SoC) design at design time, contributing to low-power systems on both algorithmic and technology level. Smart energy managem...

Power-Aware Architecture Synthesis and Optimization for Mission-Critical Embedded Systems

A power-aware system architecture must provide all the necessary mechanisms to enable its application to manage power most effectively. Designers must explore system-level architectures without hardwiring high-level policies in low-level mechanisms. Unfortunately, without tool and methodology support, today’s designers are unable to explore enough design points to make an effective power-aware ...

High Level Synthesis Methodology for Highly Testable and Nonzero Clock Skew Low Power Design